This invention relates to the art of analog-to-digital (A/D) converters, and more particularly, to A/D converters which include linearity errors.
Analog-to-digital converters (ADCs) are circuits used to convert signals from the analog domain, where the signals are represented by continuous quantities such as voltage and current, to the digital domain, where the signals are represented by numbers. These circuits can be implemented in a large number of ways. Established A/D conversion techniques include flash, delta-sigma (or sigma-delta), sub-ranging, successive approximation, and integrating.
One example of an A/D converter is an over-sampled A/D converter. Oversampled A/D converters, often denoted as xe2x80x9cdelta-sigma convertersxe2x80x9d or xe2x80x9csigma-delta convertersxe2x80x9d are well known in the art. Delta-sigma (D/S) converters have gained in popularity due primarily to their ability to realize high resolution analog-to-digital conversion in mixed signal VLSI processors.
A D/S converter essentially digitizes an analog signal at a very high sampling rate (oversampling) in order to perform a noise shaping function. Digital filtering after the noise shaping allows the D/S converter to achieve a high resolution when compared with conventional A/D converters. Decimation is thereafter used to reduce the effective sampling rate back to the xe2x80x9cNyquistxe2x80x9d rate. To gain an understanding of D/S converters, it is important to understand the operation of oversampling, noise shaping, digital filtering and decimation, the key concepts involved.
FIG. 1 shows, in block diagram form, a single bit D/S converter 10 commonly known in the art. The single bit D/S converter 10 includes a single bit D/S modulator 12 connected to a digital filter and decimation circuit 14. The D/S modulator 12 includes a summing node 16, a filter 18, a single bit A/D converter 20, and a single bit D/A converter 22. The D/A converter 22 is connected to the output of the A/D converter 20 and operates to provide feedback to the summing node 16. The summing node 16 includes a pair of inputs, one being connected to the analog input signal Vin and the other being connected to the output of the D/A converter 22.
In operation, the output of summing node 16 is low-pass filtered by filter 18 and subsequently converted into a single bit, digital signal by A/D converter 20. The single bit digital signal in turn is converted back into an analog signal by D/A converter 22 and subtracted from analog input signal Vin at summing node 16.
The single bit D/S modulator 12 converts the input signal Vin into a continuous serial stream of 1s and 0s at a rate determined by sampling clock frequency, kfS. Due to the feedback provided by the D/A converter 22 the average value output by the D/A converter 22 approaches that of the input signal Vin if the loop has enough gain.
FIG. 2A shows a schematic implementation of the single bit D/S converter of FIG. 1. In particular, FIG. 2A shows a single bit D/S converter 30 which includes a single bit D/S modulator 32 connected to a digital filter and decimation circuit 34. The single bit D/S modulator 32 includes a summing node 36, an integrator 38, a latched comparator 40 which functions as the single bit A/D converter, and a simple switching mode device 42 which functions as the single bit D/A converter.
Integrator 38 acts as a filter and has an amplitude response in the frequency domain proportional to 1/f, where f is the input frequency. Since the chopper like action of the clocked, latched comparator 40 converts the input signal to a high frequency AC signal, varying about the average value of the input Vin, the effective quantization noise at low frequencies is greatly reduced. In effect, low frequency quantization noise is xe2x80x9cshapedxe2x80x9d into higher frequencies. FIG. 2B shows the simulated noise density as a function of frequency of a D/S modulator. The y-axis is in dB and the x axis is in MHz. As can be seen, the lower noise frequencies are attenuated. The exact frequency spectrum of the resulting noise shaping depends on the sampling rate, the integrator time constant, and the order of the filter.
Clearly, a single bit, digital representation of an analog signal has very little resolution. The D/S modulator 32 of FIG. 2A is very difficult to analyze in the time domain because of the apparent randomness of the single bit nature of the data. For any given input value in a single sampling interval, data from the latched comparator 40 is virtually meaningless. A meaningful value results only when a large number of samples are averaged. If the input signal Vin is near positive full scale, it is clear that there will be more 1s than 0s in the bit stream. Likewise, for signals near the negative full scale, there will be more 0s than 1s in the bit stream. For input signals near the midscale, there will be approximately an equal number of 1s and 0s.
After the quantization noise has been shaped by the D/S modulator 32, the output of the D/S converter 30 is further processed by the digital filter and decimator circuit 34. The purpose of the digital filter is two fold. First, the digital filter acts as an anti-aliasing filter with respect to the final sampling rate, fS. Second, the digital filter filters out the higher frequency noise produced by the noise shaping process of the D/S modulator 32. Final data reduction is performed by digitally resampling the filtered output using a process called decimation. Decimation is the process of resampling at a lower rate. Decimation can be viewed as the method by which redundant signal information introduced by the oversampling process is removed.
FIG. 3 shows a multi-bit D/S converter 50 in block diagram form. The multi-bit D/S converter 50 includes a multi-bit D/S modulator 52 connected to a multi-bit digital filter and decimation circuit 54. The multi-bit D/S modulator 52 further includes a summing node 56, a filter 58, a multi-bit A/D converter 60, and a multi-bit internal D/A converter 62.
The multi-bit D/S modulator 50 of FIG. 3 operates similarly to the single-bit D/S converter of FIG. 1. The output of the summing node 56 is low-pass filtered by filter 58 and converted into a multi-bit digital signal by multi-bit internal A/D converter 60 operating at oversampling rate kfS. The multi-bit D/A converter 62 is connected via a feedback loop between the output of the multi-bit A/D converter 60 and an input node of the summing node 56, whereby the analog signal output of the D/A converter 62 is subtracted from the analog signal input Vin. Again, the output of D/A converter 62 approaches that of the analog input signal Vin due to the feedback involved. Digital filter and decimation circuit 54 removes quantization noise shaped into the higher frequencies and resamples the oversampled digital signal at rate fS.
The multi-bit D/S converter 50 of FIG. 3 provides benefits over the single bit D/S converter 10 of FIG. 1. Namely, the multi-bit D/S converter 50 provides more resolution and less quantization noise. Additionally, the multi-bit D/S converter 50 is more stable than single bit D/S converters. However, the multi-bit D/S converter suffers from linearity errors introduced by the internal multi-bit D/A converter 62. Single bit D/S converters on the other hand do not produce linearity errors.
Linearity error is the inability of the multi-bit D/A converter to accurately translate a digital input value into an analog current or voltage. In other words, given a particular digital input, the resulting analog output of the multi-bit internal D/A converter 62 approximates the digital value but is not exactly equal to the digital value. In reality, the actual analog output differs from the digital input value by an amount equal to the linearity error.
FIG. 4 shows a graphical comparison of an ideal linear vs. non-ideal, non-linear multi-bit D/A converter. The horizontal axis represents the codes or multi-bit digital signals applied to the inputs of both types of multi-bit D/A converters, ideal and non-ideal. The vertical axis represents the analog signal output therefrom. Line L represents the transfer function of the ideal or linear D/A converter. Line NL represents the transfer function of the non-ideal or non-linear D/A converter. Variations between the two lines represent the linearity errors. The distance between points on a vertical line through both line L and the line NL represent the linearity error produced by the non-ideal D/A converter for a particular input code. For example, if digital code x is input to both the ideal D/A converter and the non-ideal D/A converter, the respective outputs would be YL and YNL. The difference in voltage xcex94 Y represents the linearity error corresponding to digital code x. This linearity error is viewed as noise and degrades the ultimate signal to noise ratio of the D/S converter which contains the non-linear D/A converter. This linearity error is static in nature and independent of frequency and voltage.
The source of linearity errors can be traced to the internal current generators of the multi-bit D/A converter. FIG. 5 shows, in schematic form, a simplified D/A converter 70 employing a number of internal current generators 72. Each of the internal current generators 72 is selectively connected to an output node 74 via switches 76. Each switch 76 contains an input configured to receive one bit of the digital code inputted to the D/A converter 70. For example, switch SNxe2x88x921 is controlled by the most significant bit of the input digital code. When the most significant bit is 1, the associated current generator is connected to summing node 74. Thus, given a particular digital input code, the output of one or more of the current generators 72 is connected to the summing node 74.
If the DIA converter 70 was ideal and contained ideal current generators, current would be generated therefrom in integer units. For example, if the D/A converter 70 of FIG. 5 was an ideal 3 bit D/A converter, and a digital code inputted thereto equaled 111, the three ideal internal current generators 72 would generate 4, 2, and 1 units of current, respectively. However, internal current generators are rarely ideal. Given an input code 111, the non-ideal set of current generators, for example, might generate 4.05, 1.98, and 1.01 units of current, respectively.
The linearity error produced by the internal current generators can be further traced to a variety of causes, chief of which is the inability of integrated circuit manufacturers to form, in silicon, current generators having identical geometries. Several other causes can be related to the linearity error. Over time and use, the internal current generators may wear differently. Moreover, temperature variations may occur between the internal current generators. In any event, the physical differences between internal current generators in a D/A converter, even though slight, can produce significant errors in the translation of a digital input code into an analog equivalent.
Single bit D/A converters do not employ multiple current generators. As such, single bit D/A converters do not exhibit the non-linearity characteristics of multi-bit D/A converters. Accordingly, single bit D/S converters employing a single bit internal D/A converter, such as shown in FIG. 1, do not suffer from linearity errors. To this end, single bit D/S converters are advantageous over multi-bit D/S converters. Thus, while it is known that the resolution and stability of a multi-bit D/S converter is superior to that of a single bit D/S converter, single bit D/S converters are superior to multi-bit D/S converters to the extent that a single bit D/S converter produces less linearity error when compared to the linearity error produced by the multi-bit D/S converter. If it were not for the linearity errors caused by the internal multi-bit D/A converter, designers would generally prefer to use multi-bit D/S converters over single bit D/S converters.
It is desirable to have a multi-bit D/S converter in which the non-linearity produced by the internal D/A converter is removed or otherwise reduced.
U.S. Pat. Nos. 5,781,137; 5,781,138; 6,016,112; and 6,049,298 describe a system and method which operate to calibrate the A/D converter to eliminate or otherwise reduce linearity errors in the multi-bit A/D converter. The technique disclosed in these patents includes applying a known analog waveform, such as a pure sine wave, to an input of the A/D converter, or to a portion of the A/D converter, and generating digital signals representative of the pure sine wave. A number of the digital signals output from the converter are recorded. These recorded digital signals contain hidden information regarding the linearity errors associated with the A/D converter. The linearity error information can be extracted and used in deriving correction coefficients and constructing a linearity error correction circuit. The linearity error correction circuit then can be used to correct for linearity errors in the A/D converter.
The system and method described in the above patents utilize a waveform generator to provide an analog waveform signal to the A/D converter. The analog waveform is used to stimulate each of the current generators of the A/D converter in order to gather linearity error information about each of the current generators. In the embodiment described in the above patents, a sine wave generator is used to provide a sine wave signal to the A/D converter. However, a waveform generator is an expensive component, adding cost and reducing board area for other devices.
U.S. patent application Ser. No. 09/351,759 titled xe2x80x9cSystem and Method for Calibrating an Analog to Digital Converter Through Stimulation of Current Generatorsxe2x80x9d describes a system for calibrating an analog to digital (A/D) converter without requiring use of a waveform generator. In the method described in this application, in performing the calibration technique, a constant analog signal, such as a logical ground, or no input signal, is applied to the A/D converter, and the resulting output of the A/D converter is recorded. Thus, for example, the inputs of the A/D converter may be left floating, and the resulting output of the A/D converter is recorded. The A/D converter includes a switching element which may be comprised in the internal D/A converter of the A/D converter. During this recording, the switching element operates to change the manner in which the internal D/A converter decodes the received digital signal one or more times. The switching, element may operate a plurality of times using different switching patterns. Each of the switching patterns involve different connections between the inputs of the internal D/A converter and the respective current generators. Thus the plurality of different switching patterns ensure that a majority or all of the current generators within the D/A converter are toggled or stimulated by the constant analog input signal. The recorded digital signals thus contain hidden information regarding the linearity errors associated with a majority or all of the current generators in the internal D/A converter. This linearity error information is then used in calibrating the A/D converter.
In addition, the system and method described in the above patents requires the digital output of the modulator to be stored into a RAM before the digital output is analyzed. This analysis is rather complex and requires a xe2x80x98least squaresxe2x80x99 algorithm to be solved. This is normally done in the host computer for the computer board or device containing the A/D converter.
Because of these requirements the method described in the above patents is expensive to implement. It is desirable to be able to calibrate the modulator without the need for a precision sine wave generator, without the need for storing signals in memory, and without the need for executing a complex algorithm in a host computer.
Therefore, an improved system and method is desired for calibrating an A/D converter.
One embodiment of the present invention comprises a system and method for calibrating an analog to digital (A/D) converter without requiring use of a waveform generator, without the need for storing signals in memory, and without the need for executing a complex algorithm in a host computer. The present invention thus provides an improved A/D converter with reduced cost.
The present invention may be comprised in any of various systems which utilize a multi-bit delta sigma converter. For example, the system may be comprised in a computer-based data acquisition (DAQ) system, the system comprising a computer system and a DAQ device comprised in or coupled to the computer system. The DAQ device may include the A/D converter according to one embodiment of the present invention. The present invention may be used with any of various types of A/D converters, including integrating A/D converters, flash A/D converters, sigma-delta A/D converters, sub-ranging A/D converters, and successive approximation A/D converters, among others. The A/D converter includes, for example, one or more internal digital to analog (D/A) converters which may generate linearity errors.
In one embodiment, in performing the calibration technique, the input of the A/D converter may be left unconnected or shorted, and the coefficients may be derived by a real time analysis of the digital output, preferably using a dynamic element matching technique. This analysis may be performed by an on-board DSP used in performing decimation in the A/D converter.
The A/D converter being calibrated includes an internal D/A converter. The internal D/A converter includes a plurality M of current generators, wherein one or more of the current generators produces linearity errors in the A/D converter. The A/D converter also includes a digital correction unit that is configurable with a set of correction values. The correction values are determined from coefficients E(n) for n=0 to Mxe2x88x921, wherein each coefficient E(n) is associated with one of the current generators in the internal D/A converter.
One embodiment of the calibration method for configuring a digital correction unit for an analog to digital (A/D) converter operates as follows.
a) For each of a plurality of possible values of a coefficient E(n):
configure the digital correction unit with a current set of correction values, wherein the current set of correction values includes a value based on one of the possible values of E(n);
operate the A/D converter, wherein operation uses dynamic element matching in the internal D/A converter;
determine a noise value from output samples of the A/D converter;
b) select one of the possible values for E(n) that produces the least noise value;
perform steps a) and b) for a plurality of coefficients E to produce a final set of coefficients E; and
configure the digital correction unit with correction values based on the final set of coefficients E;
wherein the digital correction unit is useable in correcting for linearity errors in the A/D converter.
This linearity error information is then used in calibrating the A/D converter.
In another embodiment, the method for configuring the digital correction unit for an analog to digital. (A/D) converter is performed during operation of the A/D converter on received input signals of interest, i.e., during operation of the A/D converter on real data. The method comprises first receiving an input signal of interest and performing an analog low pass filter operation on the received input signal of interest. The A/D converter then operates on the received input signal of interest to produce output samples. The digital correction unit is configured with various different sets of correction values during operation of the A/D converter. For each of the different possible sets of corrections values, a digital high pass filter operation is performed on respective output samples of the A/D converter. The high pass filtered output samples are then examined, such as by determining a noise value from the output samples, and one of the sets of correction values is selected in response, e.g., the set that produces the least AC noise. The above process may be performed iteratively to produce a final set of correction values. The digital correction unit may then be configured with the final set of correction values. The configured digital correction unit is then useable in correcting for linearity errors in the A/D converter.